The evolution of electrical and electronic circuitry from component circuits to integrated circuits, particularly microelectronic integrated circuits, has presented various new considerations in circuit design. Among these considerations is the necessity of connecting circuits on the semiconductor chip to other chips or devices mounted on a printed circuit board. This is because not all connections can be made inside a single chip. Therefore, it is necessary to connect externally to different I/O areas with external conductors, such as wires. Likewise, power must be supplied to the semiconductor chips.
In order to eliminate use of wiring, chip carriers have found widespread use. The chip carrier consists of a substrate having I/O pads on either side with internal connections between the I/O pads. Referring to FIG. 1, an exemplary such prior art integrated circuit is illustrated with a semiconductor chip 10, a chip carrier 12, and a printed circuit board 14. The chip 10 is connected to I/O pads of the chip carrier 12 using, for example, solder balls 16. Likewise, opposite I/O pads of the chip carrier 12 are connected to the board using solder balls 16. As is known, interconnections can also be provided by controlled collapsible chip connectors (C4s), columns, pins or the like. The solder balls 16 on either side of the chip carrier 12 are formed in an array corresponding to the location of the I/O pads. This construction is conventionally referred to as a ball grid array (BGA). Although not shown, the chip carrier 12 may be modified to include pins brazed to the I/O pads for connection to the board 14 to define a pin grid array (PGA).
With a conventional design, such as illustrated in FIG. 1, the chip has a relatively low thermal coefficient of expansion (TCE) on the order of 3 ppm/.degree. C. The chip carrier 12 is typically constructed of a glass ceramic and also has a TCE of about 3 ppm/.degree. C. The board 14 which is typically constructed of an organic material has a substantially higher TCE on the order of about 19 ppm/.degree. C., typically. The difference in thermal expansion, particularly between the carrier 12 and the board 14, limits reliability due to fatigue from thermal cycling of the interconnections between the chip carrier 12 and the board 14. The fatigue occurs in thermal on/off cycling due to the thermal expansion mismatch between the carrier 12 and board 14 which are joined, for example, by solder. Depending on construction of the carrier 12, the chip 10 to carrier 12 interconnects can also be affected by this phenomenon.
The present invention is directed to overcoming one or more of the problems discussed above, in a novel and simple manner.